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? semiconductor components industries, llc, 2016 july, 2016 ? rev. 1 1 publication order number: NCP81248/d NCP81248 three-rail controller with intel proprietary interface for imvp8 cpu applications the NCP81248 contains a two?phase, and two single?phase buck regulator controllers optimized for intel imvp8 compatible cpus. the two?phase controller combines true differential voltage sensing, differential inductor dcr current sensing, input voltage feed?forward, and adaptive voltage positioning to provide accurately regulated power for imvp8 cpu. the two single?phase controllers make use of on semiconductor?s patented high performance rpm operation. rpm control maximizes transient response while allowing smooth transitions between discontinuous frequency scaling operation and continuous mode full power operation. the single?phase rails have a low offset current monitor amplifier with programmable offset compensation for high accuracy current monitoring. features common to all rails ? vin range 4.5 v to 25 v ? startup into pre?charged loads while avoiding false ovp ? digital soft start ramp ? adjustable vboot (except rail3) ? high impedance differential output voltage amplifiers ? dynamic reference injection ? programmable output voltage slew rates ? dynamic vid feed?forward ? differential current sense amplifiers for each phase ? programmable adaptive voltage positioning (avp) ? switching frequency range of 200 khz ?1.2 mhz ? digitally stabilized switching frequency ? ultrasonic operation two?phase rail features ? supports intel proprietary interface addresses 00 and 01 ? current mode dual edge modulation for fastest initial response to transient loading ? high performance operational error amplifier ? accurate total summing current amplifier ? phase?to?phase dynamic current balancing ? power saving phase shedding single?phase rail features ? supports intel proprietary interface addresses 00, 01, 02 and 03 ? high performance rpm control system ? low offset iout monitor ? zero droop capable other features ? psys input monitor ? thermal monitors for three intel proprietary interface addresses ? these devices are pb?free, halogen free/bfr free and are rohs compliant device package shipping ordering information NCP81248mntxg qfn48 (pb?free) 2500 / tape & reel qfn48 case 485ba www. onsemi.com 48 1 ncp81243 = specific device code f = wafer fab code a = assembly location wl = wafer lot yy = year ww = work week = pb?free package NCP81248 fawlyyww marking diagram ?for information on tape and reel specifications, in - cluding part orientation and tape sizes, please refe r to our tape and reel packaging specification s brochure, brd8011/d.
NCP81248 www. onsemi.com 2 NCP81248 pwm_1b vsn_2ph vcc iout_2ph 13 1 drvon diffout_2ph 2 sclk fb_2ph 3 alert# comp_2ph 4 sdio ilim_2ph 5 vr_hot# cscomp_2ph 6 iout_1a cssum_2ph 7 36 csp_1a csref_2ph 8 35 csn_1a csp2_2ph 9 34 ilim_1a csp1_2ph 10 33 comp_1a tsense_2ph 11 32 vsn_1a vrmp 12 31 30 29 vsp_2ph rosc_coregt 14 psys rosc_saus 15 vsp_1b pwm1_2ph 16 vsn_1b pwm2_2ph 17 comp_1b iccmax_2ph 18 ilim_1b iccmax_1a 19 csn_1b iccmax_1b 20 csp_1b addr_vboot 21 48 iout_1b pwm_1a 22 47 vr_rdy tsense_1ph 23 46 en vsp_1a 24 45 44 43 42 28 (top view) tab: ground 27 26 41 40 39 38 37 25 figure 1. NCP81248 imvp8 ncp81382 drmos vcc_rail1 vcc_rail2 vcc_rail3 svid ncp81382 drmos ncp81382 drmos ncp81382 drmos figure 2. typical drmos application diagram intel
NCP81248 www. onsemi.com 3 5v smod# zcd_en vccd vcc pwm disb# vin vsw boot phase ncp81382 t 5v smod# zcd_en vccd vcc pwm disb# vin vsw boot phase ncp81381 5v smod# zcd_en vccd vcc pwm disb# vin vsw boot phase ncp81380 t 5v smod# zcd_en vccd vcc pwm disb# vin vsw boot phase ncp81381 5v vcc pwm_1a drvon csp_1a csn_1a vsp_1a vsn_1a pwm1_2ph csp1_2ph csref_2ph csp2_2ph cssum_2ph ilim_2ph cscomp_2ph pwm2_2ph vsp_2ph vsn_2ph tsense_2ph tsense_1ph csp_1b pwm_1b vsp_1b vsn_1b csn_1b ground t comp_1a ilim_1a iout_1a vrhot# sdio alert# sclk vr_rdy diffout_2ph fb_2ph comp_2ph iout_2ph rosc_coregt rosc_saus iccmax_2ph iccmax_1a iccmax_1b comp_1b ilim_1b iout_1b addr_vboot psys vrmp en t t vccio vccio vin skt_sns + skt_sns ? skt_sns + skt_sns ? skt_sns + skt_sns ? vcc_rail2 vcc_rail3 vcc_rail1 figure 3. application schematic
NCP81248 www. onsemi.com 4 programming detection monitor amp dac ovp comparators max overcurrent overcurrent current current comparators uvlo & en error interface svid mux monitor thermal psys 46 iccmax_2ph 18 vrhot# 31 sdio 32 alert# 33 sclk 34 iccmax_1a 19 rosc_saus 15 rosc_coregt 14 vrmp 12 iccmax_1b 20 vsp_2ph 47 _ + sense balance current amplifiers amp & logic state power pwm adc generators dac oscillator & ramp generators logic vr ready data registers iph2 current dac ovp iph1 ocp forward 1.3v enable gate amp comp vsn vsp ps# pwm1_2ph 16 pwm2_2ph 17 iout_2ph pwm2 1.3v _ _ + vr_rdy 38 vsn vsp pwm1 buffer diffout_2ph 2 csp2_2ph 9 csp1_2ph 10 drvon 35 csref_2ph 8 cssum_2ph 7 cscomp_2ph 6 ilim_2ph 5 iout_2ph 1 fb_2ph 3 vsn_2ph 48 comp_2ph 4 enable ps# drvon ps# ps# vrmp cscomp csref addr_vboot 21 iout feed? zero ovp enable enable ovp ocp ovp drvon ocp ovp diff tsense_2ph 11 tsense_1ph 23 iout_1a iout_1b vcc 13 en 37 ground 49 figure 4. 2?phase rail block diagram
NCP81248 www. onsemi.com 5 vsp_1a 24 pwm_1a 22 comp_1a 26 csp_1a 29 csn_1a 28 ilim_1a 27 iout_1a 30 vsn_1a 25 programming detection monitor comparators ovp ref overcurrent overcurrent current current sense amp pwm generator dac ramp generator current dac ocp forward ps# vsn vsp dac dac vrmp iout feed? zero ovp curr dac feedforward current droop current ocp ref pwm ramp freq from svid interface ocp _ + av=1 gm gm gm gm comp ovp drvon figure 5. single phase ?a? block diagram vsp_1b 45 pwm_1b 36 comp_1b 43 csp_1b 40 csn_1b 41 ilim_1b 42 iout_1b 39 vsn_1b 44 programming detection monitor comparators ovp ref overcurrent overcurrent current current sense amp pwm generator dac ramp generator current dac ocp forward ps# vsn vsp dac dac vrmp iout feed? zero ovp curr dac feedforward current droop current ocp ref pwm ramp freq from svid interface ocp _ + av=1 gm gm gm gm comp ovp drvon figure 6. single phase ?b? block diagram
NCP81248 www. onsemi.com 6 table 1. NCP81248 pin descriptions pin no. symbol description 1 iout_2ph iout gain programming pin for the 2?phase regulator 2 diffout_2ph output of the 2?phase regulator?s output differential remote sense amplifier 3 fb_2ph error amplifier voltage feedback input for the 2?phase regulator 4 comp_2ph output of the error amplifier and the inverting inputs of pwm comparators for the two?phase regulator 5 ilim_2ph over?current monitor input for the 2?phase regulator ?? programmed with a resistor to cscomp_2ph 6 cscomp_2ph output of total?current?sense amplifier for the 2?phase regulator 7 cssum_2ph inverting input of total?current?sense amplifier for the 2?phase regulator 8 csref_2ph total?current?sense amplifier reference voltage input for the 2?phase regulator 9 csp2_2ph non?inverting input to 2?phase regulator phase 2 current?balance amplifier 10 csp1_2ph non?inverting input to 2?phase regulator phase 1 current?balance amplifier 11 tsense_2ph temperature sense input for the 2?phase regulator (see rail configuration table) 12 vrmp vin feed?forward input for compensating modulator ramp?slopes. the current fed into this pin is used to control the ramp of the pwm slopes. also, the input monitoring vin for undervoltage (uvlo) 13 vcc power for the internal control circuits. a decoupling capacitor must be connected from this pin to ground 14 rosc_coregt switching frequency program input for rails configured as rail1 and rail2 15 rosc_saus switching frequency program input for the 1?phase rail configured as rail3 16 pwm1_2ph 2?phase regulator phase 1 pwm output 17 pwm2_2ph 2?phase regulator phase 2 pwm output 18 iccmax_2ph during startup, the iccmax of the 2?phase regulator is programmed by a pull?down resistor on this pin 19 iccmax_1a during startup, the iccmax of 1?phase regulator 1a is programmed by a pulldown resistor on this pin 20 iccmax_1b during startup, the iccmax of 1?phase regulator 1b is programmed by a pulldown resistor on this pin 21 addr_vboot during startup, a resistor to gnd programs intel proprietary interface addresses and vboot options for all three rails 22 pwm_1a 1?phase regulator 1a pwm output 23 tsense_1ph temperature sense input for 1?phase regulator. (see rail configuration table) 24 vsp_1a positive input of 1?phase regulator 1a differential output voltage sense amplifier 25 vsn_1a negative input of 1?phase regulator 1a differential output voltage sense amplifier 26 comp_1a compensation for 1?phase regulator 1a 27 ilim_1a current?limit for 1?phase regulator 1a is programmed by a pull?down resistor on this pin 28 csn_1a negative input of 1?phase regulator 1a differential current sense amplifier 29 csp_1a positive input of 1?phase regulator 1a differential current sense amplifier pull this pin to vcc to disable 1?phase regulator 1a 30 iout_1a iout gain programming pin for 1?phase regulator 1a 31 vr_hot# open drain output for an over?temperature condition detected on any tsense input 32 sdio serial vid data interface 33 alert# serial vid alert# 34 sclk serial vid clock 35 drvon enable output for external discrete fet drivers and/or on semiconductor drmos. 36 pwm1b 1?phase regulator 1b pwm output
NCP81248 www. onsemi.com 7 table 1. NCP81248 pin descriptions pin no. description symbol 37 en enable. high activates all configured rails 38 vr_rdy open drain output. high indicates all three rails are ready to accept intel proprietary interface com- mands 39 iout_1b iout gain programming pin for 1?phase regulator 1b 40 csp_1b positive input of 1?phase regulator 1b differential current sense amplifier pull this pin to vcc to disable 1?phase regulator 1b 41 csn_1b negative input of 1?phase regulator 1b differential current sense amplifier 42 ilim_1b current?limit for 1?phase regulator 1b is programmed by a pull?down resistor on this pin 43 comp_1b compensation for 1?phase regulator 1b 44 vsn_1b negative input of 1?phase regulator 1b differential output voltage sense amplifier 45 vsp_1b positive input of 1?phase regulator 1b differential output voltage sense amplifier 46 psys system power signal input. resistor to ground needed for scaling. when the NCP81248 is configured with a rail4, this input is a temperature monitor. (see rail configuration table) 47 vsp_2ph positive input of 2?phase regulator differential output voltage sense amplifier 48 vsn?2ph negative input of 2?phase regulator differential output voltage sense amplifier table 2. maximum ratings rating symbol min max unit pin voltage range (note 1) vsn_x ?0.3 +0.3 v pin voltage range (note 1) vcc ?0.3 6.5 v pin voltage range (note 1) iout_x ?0.3 2.5 v pin voltage range (note 1) vrmp ?0.3 +25 v pin voltage range (note 1) all other pins ?0.3 vcc + 0.3 v junction temperature t j(max) ?40 125 c operating ambient temperature t j(op) ?40 100 c storage temperature range t stg ?40 150 c moisture sensitivity level qfn package msl 1 ? lead temperature soldering reflow (smd styles only), pb?free versions (note 3) t sld 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. all signals referenced to gnd unless noted otherwise. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec?q100?002 (eia/jesd22?a114) esd machine model tested per aec?q100?003 (eia/jesd22?a115) latchup current maximum rating: 150 ma per jedec standard: jesd78 3. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d. 4. pin ratings referenced to vcc apply with vcc at any voltage within the vcc pin voltage range.
NCP81248 www. onsemi.com 8 table 3. thermal characteristics rating symbol value unit thermal characteristic qfn package (note 5) r ja 68 c/w thermal characteristic qfn package (note 5) r jc 8 c/w 5. jesd 51?5 (1s2p direct?attach method) with 0 lfm table 4. electrical characteristics ? elements common to single & 2?phase rails (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?40 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter symbol test conditions min typ max unit vcc input supply supply voltage range 4.75 5.25 v quiescent current en = high, t a = 100 c 28 32 ma en = low, t a = 25 c 30 50 a uvlo threshold vcc rising 4.5 v vcc falling 4 v uvlo hysteresis (note 6) 180 290 mv vrmp uvlo threshold vrmp rising 3.95 4.25 v vrmp falling 3 3.24 v uvlo hysteresis (note 6) 500 710 mv ramp feed?forward control range range in which the ramp slope is affected by vrmp voltage 5 20 v enable input enable high input leakage current external 1k pull?up to 3.3 v 1.0 a activation level v upper 0.8 v deactivation level v lower 0.3 v total hysteresis (note 6) v rising ? v falling 295 mv enable delay time ? rising time from enable transitioning high to drvon going high 1.0 2.1 2.5 ms enable delay time ? falling (note 6) time from enable transitioning low to drvon below 0.8 v 190 ns phase detection csp pin pulldown current (note 6) pulldown applied only prior to softstart 20 a csp pin threshold voltage 4.5 v phase detect timer (note 6) 1.8 ms dac slew rate soft start slew rate 15 mv/ s slew rate slow 15 mv/ s slew rate fast 30 mv/ s drvon output high voltage sourcing 500 a 3.0 v output low voltage sinking 500 a 0.1 v
NCP81248 www. onsemi.com 9 table 4. electrical characteristics ? elements common to single & 2?phase rails (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?40 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min test conditions symbol drvon rise time cl (pcb) = 20 pf, vo = 10% to 90% 150 ns fall time 2.5 internal pull up resistance 2.5 k internal pull down resistance en = low 50 k pwm outputs output high voltage sourcing 500 a vcc? 0.2v v output mid voltage ps2, no load 1.9 2.0 2.1 v output low voltage sinking 500 a 0.7 v rise and fall time (note 6) cl (pcb) = 50 pf, vo = 10% to 90% 8 ns vr_rdy output output low saturation voltage i vr_rdy = 4 ma 0.3 v rise time external pull?up of 1 k to 3.3 v c tot = 45 pf, vo = 10% to 90% 120 ns fall time external pull?up of 1 k to 3.3 v c tot = 45 pf, vo = 90% to 10% 25 ns output leakage current when high vr_rdy= 5.0 v ?1.0 1.0 a vr_hot# output low voltage i vrhot = 4 ma 0.3 v output leakage current high impedance state ?1.0 1.0 a adc linear input voltage range 0 2.00 v differential nonlinearity (dnl) highest 8?bits 1 lsb conversion time 7.4 s conversion rate 136 khz total unadjusted error (tue) ?1.25 +1.25 % power supply sensitivity 1 % round robin time 59 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. guaranteed by design or characterization data. not tested in production.
NCP81248 www. onsemi.com 10 table 5. electrical characteristics ? two phase regulator (v cc = 5.0 v, v en = 2.0 v, c vcc =0.1 f unless specified otherwise) min/max values are valid for the temperature range ?40 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter symbol test conditions min typ max unit differential summing amplifier input bias current ? vsp vsp = 1.3 v ?1 1 a input bias current ? vsn vsn = 0 v ?25 25 na vsp input voltage range ?0.3 3.0 v vsn input voltage range ?0.3 0.3 v ?3 db bandwidth (note 7) cl = 20 pf to gnd, rl = 10 k to gnd 18 mhz closed loop dc gain v vsp ? v vsn = 0.5 to 1.3 v 1.0 v/v error amplifier input bias current v fb = 1.3 v ?400 400 na open loop dc gain (note 7) cl = 20 pf to gnd, rl = 10 k to gnd 80 db open loop unity gain bandwidth (note 7) cl = 20 pf to gnd, rl = 10 k to gnd 20 mhz slew rate (note 7) vin = 100 mv, g = ?10v/v, vout = 1.5 v ? 2.5v, cl = 20 pf to gnd, dc load = 10k to gnd 30 v/ s maximum output voltage i source = 2.0 ma 3.5 v minimum output voltage i sink = 2.0 ma 1 v current summing amplifier offset voltage (note 7) v os ?375 375 v input bias current v cssum = v csref = 1 v ?7.5 7.5 na open loop gain (note 7) 80 db unity gain bandwidth (note 7) c l = 20 pf to gnd, r l = 10 k to gnd 10 mhz maximum cscomp output voltage isource = 2 ma 3.5 v minimum cscomp output voltage isink = 500 a 100 mv isink = 25 a 7 30 mv current balance amplifiers input bias current v csp1 = v csp2 = v csref = 1.2 v ?50 50 na common mode input voltage range v csp1 = v csp2 = v csref 0 2.3 v differential input voltage range v csref = 1.2 v ?100 100 mv input offset voltage matching v csp1 = v csp2 = v csref = 1.2 v deviation from average offset ?1.5 1.5 mv current sense amplifier gain 0 v < v cspx ? v csref < 0.1 v 5.7 6.0 6.3 v/v current sense gain matching 10 mv < v cspx ? v csref < 30 mv ?4 4 % ?3 db bandwidth (note 7) 8 mhz iout output input referred offset voltage ilim to csref ?2.75 2.75 mv output source current ilim sink current = 20 a 190 a current gain i iout / i ilim ; r ilim = 20k, r iout = 5.0k , dac = 0.8 v, 1.25 v, 1.52v 9.5 10 10.5 a/ a
NCP81248 www. onsemi.com 11 table 5. electrical characteristics ? two phase regulator (v cc = 5.0 v, v en = 2.0 v, c vcc =0.1 f unless specified otherwise) min/max values are valid for the temperature range ?40 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min test conditions symbol overcurrent protection ilim threshold current (delayed ocp shutdown) i cl0 9.0 10 11 a i cl1 6.7 a ilim threshold current (immediate ocp shutdown) i clm0 13.5 15 16.5 a i clm1 10 a shutdown delay (immediate) 300 ns shutdown delay (delayed) t ocpdly 50 s ilim offset voltage v ilim ? v csref ; ilim sourcing 15 a ?2 2 mv output over voltage & under voltage protection (ovp & uvp) absolute over voltage threshold v ovabs2 csref voltage during softstart 2 v over voltage threshold above dac v ovp2 v vsp ? v vsn ? vid rising 365 430 mv over voltage delay (note 7) v vsp ? v vsn rising to pwm low 25 ns under voltage v uvm v vsp ? v vsn ? vid falling ?370 ?295 ?225 mv under?voltage delay (note 7) v vsp ? v vsn falling to vr_rdy falling 5 s oscillator switching frequency range 200 ? 1200 khz modulators (pwm comparators) 0% duty cycle comp voltage when the pwm outputs remain lo 1.3 v 100% duty cycle comp voltage when the pwm outputs remain hi vrmp = 12.0 v 2.5 v pwm phase angle error 15 deg tsense_2ph alert# assert threshold 25 c to 100 c 488 mv alert# de?assert threshold 25 c to 100 c 510 mv vrhot assert threshold 25 c to 100 c 469 mv vrhot rising threshold 25 c to 100 c 489 mv bias current 25 c to 100 c 116 120 124 a iccmax pin bias current i mxbias2 applied only after enabling, and prior to softstart. 9.63 9.98 10.32 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. guaranteed by design or characterization data. not tested in production.
NCP81248 www. onsemi.com 12 table 6. electrical characteristics ? single phase regulators (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?40 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter symbol test conditions min typ max unit error amplifier input bias current vsp ? see droop output vsn ?25 25 na vsp input voltage range ?0.3 3.0 v vsn input voltage range ?0.3 0.3 v gain gm ea 1.2 1.6 1.9 ms input offset ?500 500 v open loop gain (note 8) load = 1 nf in series with 1 k in parallel with 10 pf to ground 73 db source current input differential ?200 mv 200 a sink current input differential 200 mv 200 a ?3db bandwidth (note 8) load = 1 nf in series with 1 k in parallel with 10 pf to ground 15 mhz current sense amplifier input bias current v csp = v csn = 1.2 v ?50 50 na common mode input range (note 8) v csp = v csn 0 2.0 v common mode rejection v csp = v csn = 0.5 v to 1.2 v 45 80 db differential input voltage range (note 8) v csn = 1.2 v ?70 70 mv ?3db bandwidth (note 8) 6 mhz iout gain gm iout 0 mv v csp ? v csn 25 mv; 25 c 0.95 1.0 1.05 ms output offset current 0 v iout 2 v ?250 250 na maximum output current (note 8) 0 v iout 2 v 70 a maximum output voltage (note 8) i iout = ?100 a 2.1 v droop output (vsp pin) gain gm vsp 0 v v csp ? v csn 0.1 v 0.94 1.0 1.06 ms output offset current 0.5 v vsp 1.2 v ?1100 1100 na maximum output current (note 8) 0 v vsp 1.8 v 70 a output voltage range (note 8) i vsp = ?100 a 1.8 v overcurrent protection (ilim pin) gain gm ilim 18 mv v csp ? v csn 50 mv 0.90 1.0 1.08 ms output offset current v ilim = 1.3 v ?1.0 1.0 a maximum output current (note 8) 0 v ilim 1.3 v 70 a maximum output voltage (note 8) i ilim = ?100 a 1.4 v activation threshold voltage v cl 1.275 1.3 1.325 v activation delay (note 8) 250 ns oscillator switching frequency range 200 1200 khz zcd comparator offset accuracy (note 8) referred to v csp ? v csn 1.5 mv
NCP81248 www. onsemi.com 13 table 6. electrical characteristics ? single phase regulators (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?40 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min test conditions symbol output over voltage & under voltage protection (ovp & uvp) over voltage threshold v ovp1 v vsp ? v vsn ? vid rising 365 430 mv absolute over voltage threshold v ovabs1 csn voltage during soft?start 2 v over voltage delay (note 8) v vsp rising to pwm low 25 ns over voltage vr_rdy delay (note 8) v vsp rising to vr_rdy low 350 ns under voltage threshold v uvm1 v vsp ? v vsn ? vid falling ?400 ?295 400 mv under?voltage hysteresis (note 8) 25 mv under?voltage blanking delay (note 8) v vsp ? v vsn falling to vr_rdy falling 5 s tsense_1ph alert# assert threshold 25 c to 100 c 490 mv alert# de?assert threshold 25 c to 100 c 502 mv vrhot assert threshold 25 c to 100 c 476 mv vrhot rising threshold 25 c to 100 c 480 mv bias current 25 c to 100 c 116 120 124 a iccmax pins bias current (note 8) i mxbias1a applied only after enabling, and prior to soft?start. 9.53 9.98 10.33 a i mxbias1b 9.53 9.94 10.33 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 8. guaranteed by design or characterization data. not tested in production.
NCP81248 www. onsemi.com 14 general information the NCP81248 is a three?rail imvp8 controller with an intel proprietary control interface. serial vid interface (intel proprietary interface) for intel proprietary interface communication details please contact intel ? , inc. the table below specifies the addr_vboot pin pulldown resistor (1% tolerance required) needed to program all possible supply rail configurations. four boot voltages are available for all rails except for the sa rail. rail configuration table ad- dr_vboot resistance system rail configuration rail1 rail2 rail3 phase count tsense _1ph boot voltag e phase count tsense _2ph boot voltag e phase count boot voltage a/b a/b 10k 1 a 0 v 2 or 1 0 v 1 b 1.05 v 1+2+1 rail1+rail2+r ail3 16.2k 1 a 1.2 v 2 or 1 1.2 v 1 b 22.1k 1 a 1.05 v 2 or 1 1.05 v 1 b 28.7k 1 a 1.0 v 2 or 1 1.0 v 1 b ad- dr_vboot resistance rail1 rail2 rail3 configuration phase count tsense _2ph boot voltag e phase count tsense _1ph boot voltag e phase count boot voltage a/b a/b 35.7k 2 or 1 0 v 1 a 0 v 1 b 1.05 v 2+1+1 rail1+rail2+r ail3 43.2k 2 or 1 1.2 v 1 a 1.2 v 1 b 51.1k 2 or 1 1.05 v 1 a 1.05 v 1 b 61.9k 2 or 1 1.0 v 1 a 1.0 v 1 b ad- dr_vboot resistance rail1 rail2 rail3 configuration phase count tsense _1ph boot voltag e phase count tsense _2ph boot voltag e phase count boot voltage a/b a/b 71.5k 1 b 0 v 2 or 1 0 v 1 a 1.05 v 1+2+1 rail3+rail2+r ail1 82.5k 1 b 1.2 v 2 or 1 1.2 v 1 a 95.3k 1 b 1.05 v 2 or 1 1.05 v 1 a 110k 1 b 1.0 v 2 or 1 1.0 v 1 a ad- dr_vboot resistance rail1 rail2 rail4 configuration phase count tsense psys boot voltag e phase count tsense _2ph boot voltag e phase count tsense _1ph boot voltage a/b a/b 127k 1 b 0 v 2 or 1 0 v 1 a 0 v 1+2+1 rail1+rail2+r ail4 143k 1 b 1.2 v 2 or 1 1.2 v 1 a 1.2 v 165k 1 b 1.05 v 2 or 1 1.05 v 1 a 1.05 v 187k 1 b 1.0 v 2 or 1 1.0 v 1 a 1.0 v
NCP81248 www. onsemi.com 15 start up following the rise of v cc above the uvlo threshold, externally programmed configuration data is collected, and the pwm outputs are set to mid?level to prepare the gate drivers of the power stages for activation. when the controller is enabled, drvon is asserted (high) to activate the gate drivers. a digital counter steps the dac up from zero to the target voltage based on the soft start slew rate in the spec table. as the dac ramps, the pwm outputs of each rail will change from mid?level to high when the first pwm pulse for that rail is produced. when the controller is disabled, the pwm signals return to mid?level. figure 7. drvon phase count, rail disabling & psys disabling detection sequence during start?up, the number of operational phases of the 2?phase rail, and whether or not each single?phase rail becomes active and responds to an address call on the intel proprietary interface bus, is determined by the internal circuitry monitoring the csp inputs. normally, the 2?phase rail operates with both phases. if csp2_2ph is externally pulled to v cc with a resistor during startup, the two?phase rail operates as a single?phase rail, and does not use pwm2_2ph and csp2_2ph. likewise, if csp of either or both single?phase rails is pulled to v cc during startup, it is disabled and will not respond to any address calls on the intel proprietary interface bus. also, whether or not the psys function is active and responds to an address call on the intel proprietary interface bus is determined by the internal circuitry monitoring the psys input. tying the psys input to v cc will cause the NCP81248 to not respond to any calls to address 0dh on the intel proprietary interface bus. switching frequency switching frequencies between 200 khz and 1.2 mhz are programmed at startup with pulldown resistors on pins 14 and 15. the 1a and 2?phase regulators are programmed to the same switching frequency by the pin 14 resistor, and the rail3 or rail1 (usually the 1b regulator) is programmed by the pin 15 resistor.
NCP81248 www. onsemi.com 16 figure 8. switching frequency vs. rosc resistance the rail1/rail2 oscillator serves as the master clock for the 2?phase rail ramp generator when configured for 2?phase operation, and as a frequency stabilization clock for a single phase rail and for the 2?phase rail when it is configured for single phase operation. the sa/us oscillator serves as a frequency stabilization clock for the rail3. the formulas to calculate the switching frequency and programming resistances are: r osc 2*10 11 * frequency ?1.192 [ ] (eq. 1) frequency 3*10 9 * frequency ?0.838 [hz] (eq. 2) input voltage feed?forward (vramp pin) ramp generator circuits are provided for both the dual?edge modulator (only when 2?phases are operating) and three rpm modulators. the ramp generators implement input voltage feed?forward control by varying the ramp slopes proportional to the vrmp pin voltage. the vrmp pin also has a 4 v uvlo function, which is active only after the controller is enabled. the vrmp pin is high impedance input when the controller is disabled. for 2?phase operation, the dual?edge pwm ramp amplitude is changed according to the following, v ramp_pp 0.1 * v vrmp (eq. 3) vin comp?il duty vramp_pp figure 9.
NCP81248 www. onsemi.com 17 interleaving in order to minimize stress on the input voltage and simplify input filter design, the NCP81248 monitors the phase?angle relationship between the rails. small adjustments are made to keep phases of both rails from turning on at the same time. but if a phase must turn on to respond to a sudden load increase, it will do so even if the other rail has a phase that is turned on. this feature is intended to reduce loading on the input supply during steady?state conditions. if either rail is operating in dcm mode, this feature is disabled. programming two?phase rail icc_max a resistor to ground on the iccmax_2ph pin programs the register for the 2?phase rail at the time the part is enabled. current i mxbias2 is sourced from this pin to generate a voltage on the program resistor. the resistor value should be no less than 10k. icc_max 21h r*i mxbias2 * 128 a 2v (eq. 4) programming tsense two temperature sense inputs are provided ? one for the 2?phase rail, and the other for single?phase rail 1a. a precision current is sourced out the output of the tsense pins to generate a voltage on the temperature sense networks. the voltages on the temperature sense inputs are sampled by the internal a/d converter. a 100k ntc similar to the murata ncp15wf104e03rc should be used. rcomp1 in the f ollowing figure is optional, and can be used to slightly change the hysteresis. see the specification table for the thermal sensing voltage thresholds and source current. rcomp2 8.2k rntc 100k cfilter 0.1uf agnd agnd rcomp1 0.0 tsense figure 10. ultrasonic mode the switching frequency of a rail in dcm will decrease at very light loads. ultrasonic mode forces the switching frequency to stay above the audible range. two?phase rail remote sense amplifier a high performance high input impedance true differential amplifier is provided to accurately sense regulator output voltage. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points. the remote sense amplifier takes the difference of the output voltage with the dac voltage and adds the droop voltage. v diffout v vsp v vsn 1.3 v v dac (eq. 5) v droop v csref this signal then goes through a standard error compensation network and into the inverting input of the error amplifier. two?phase rail voltage compensation the remote sense amplifier output feeds a type iii compensation network formed by the error amplifier and external tuning components. the non?inverting input of the error amplifier is connected to the same reference voltage used to bias the remote sense amplifier output. figure 11. two?phase rail differential current feedback amplifiers each phase of the two?phase rail has a low offset, differential amplifier to sense the current of that phase in order to balance current. the csref and cspx pins are high impedance inputs, but it is recommended that any external filter resistor rcsn does not exceed 10 k to avoid offset due to leakage current. it is also recommended that the voltage sense element be no less than 0.5 m for best current balance. the external filter rcsn and ccsn time constant should match the inductor l/dcr time constant, but fine tuning of this time constant is generally not required. phase current signals are summed with the comp or ramp signals at their respective pwm comparator inputs in order to balance phase currents via a current mode control approach.
NCP81248 www. onsemi.com 18 ccsn rcsn dcr lphase 1 2 swnx vout cspx csnx figure 12. r csn l phase c csn * dcr [ ] two?phase rail total current sense amplifier the NCP81248 uses a patented approach to sum the phase currents into a single, temperature compensated, total current signal. this signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. the rref(n) resistors average the voltages at the output terminals of the inductors to create a low impedance reference voltage at csref. the rph resistors sum currents from the switchnodes to the virtual csref potential created at the cssum pin by the amplifier. the total current signal is the difference between the cscomp and csref voltages. the amplifier filters, and amplifies, the voltage across the inductors in order to extract only the voltage across the inductor series resistances (dcr). an ntc thermistor (rth) in the feedback network placed near the phase 1 inductor senses the inductor temperature, and compensates both the dc gain and the filter time constant for the change in dcr with temperature. the phase 1 inductor is chosen for the thermistor location so that the temperature of the inductor providing current in the ps1 power mode. cscomp cssum csref _ + rcs2 csn2 csn1 swn1 swn2 rref2 rref1 rph1 rph2 rcs1 ccs1 ccs2 rth cref riout rilim ilim buffer iout to remote sense amplifier controller comparators current limit mirror current figure 13. the dc gain equation for the dc total current signal is: v cscomp?csref r cs2 r cs1 *rth r cs1 rth rph * iout total * dcr (eq. 6) set the dc gain by adjusting the value of the rph resistors in order to make the ratio of total current signal to output current equal the desired loadline. the values of rcs1 and rcs2 are set based on the effect of temperature on both the thermistor and inductor, and may need to be adjusted to eliminate output voltage temperature drift with the final product enclosure and cooling. the pole frequency of the cscomp filter should be set equal to the zero of the output inductor. this causes the total current signal to contain only the component of inductor voltage caused by the dcr voltage, and therefore to be proportional to inductor current. connecting ccs2 in parallel with ccs1 allows fine tuning of the pole frequency using commonly available capacitor values. it is best to perform fine tuning during transient testing. f z dcr@25c 2* *l phase [hz] (eq. 7) f p 1 2* * rcs2 rcs1*rth@25c rcs1 rth@25c ( ccs1 ccs2 ) [hz] (eq. 8) the value of the c ref capacitor (in nf) on the csref pin should be: c ref 0.02 * r ph r ref [nf] (eq. 9)
NCP81248 www. onsemi.com 19 two?phase rail loadline programming (droop) an output loadline is a power supply characteristic wherein the regulated (dc) output voltage decreases proportional to load current. this characteristic can reduce the output capacitance required to maintain output voltage within limits during load transients faster than those to which the regulation loop can respond. in the NCP81248, a loadline is produced by adding a signal proportional to output load current (v droop ) to the output voltage feedback signal ? thereby satisfying the voltage regulator at an output voltage reduced proportional to load current. the loadline is programmed by setting the gain of the total current sense amplifier such that the total current signal is equal to the desired output voltage droop. two?phase rail programming the current limit the current limit thresholds are programmed with a resistor between the ilim and cscomp pins. the NCP81248 generates a replica of the csref pin voltage at the ilim pin, and compares ilim pin current to i cl0 and i clm0 . the NCP81248 latches off if ilim pin current exceeds i cl0 (i cl1 for ps1, ps2, and ps3) for t ocpdly , and latches off immediately if ilim pin current exceeds i clm0 (i clm1 for ps1, ps2 and ps3). set the value of the current limit resistor r limit according to the desired current limit iout limit . r limit rcs2 rcs1*rth rcs1 rth rph * iout limit * dcr 10 (eq. 10) two?phase rail programming iout the iout pin sources a current proportional to the ilim current. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a pull?up resistor from 5 v v cc can be used to of fset the iout signal positive if desired. r iout 2.0 v * r limit 10 * rcs2 rcs1*rth rcs1 rth rph * iout icc_max * dcr [ ] (eq. 11) two?phase rail programming dac feed?forward filter the NCP81248 outputs a pulse of current from the vsn pin upon each increment of the internal dac following a dvid up command. a parallel rc network inserted into the path from vsn to the output voltage return sense point, vss_sense, causes these current pulses to temporarily decrease the voltage between vsp and vsn. this ca uses the output voltage during dvid to be regulated slightly higher, in order to compensate for the response of the droop function to current flowing into the charging output capacitors. in the following equations, cout is the total output capacitance of the system. vsp vsn _ + vss_sense vcc_sense rff cff dvid up controller amplifier remote sense dac increment _ + vsn dac current pulses figure 14. r ff loadline * cout 9.35 * 10 ?10 [ ] (eq. 12) c ff 200 r ff [nf] (eq. 13) two?phase rail pwm comparators the noninverting input of each comparator (one for each phase) is connected to the summation of the error amplifier output (comp) and each phase current (i l *dcr*phase balance gain factor). the inverting input is connected to the triangle ramp voltage of that phase. the output of the comparator generates the pwm output.
NCP81248 www. onsemi.com 20 the main rail pwm pulses are centered on the valley of the triangle ramp waveforms and both edges of the pwm signals are modulated. during a transient event, the duty cycle can increase rapidly as the error amp signal increases with respect to the ramps, to provide a highly linear and proportional response to the step load. single?phase rails the architecture of the two single?phase rails makes use of a digitally enhanced , high performance , current mode rpm control method that provides excellent transient response while minimizing transient aliasing. the average operating frequency is digitally stabilized to remove frequency drift under all continuous mode operating conditions. features of the single?phase rails ? supports intel proprietary interface addresses 00, 01, 02, 03 ? adjustable vboot ? programmable slew rate ? dynamic vid feed?forward ? high performance rpm control system ? programmable droop gain (zero droop capable) ? low offset iout monitor ? thermal monitor ? digitally controlled operating frequency ? ultrasonic operation single?phase rail frequency programming one of the two single?phase rails has frequency programmed by the rosc_coregt pin, and the other has frequency programmed by the rosc_saus pin. rosc_coregt always controls the frequency of the rail1 and rail2 unless there are two rail2. in that case, rosc_coregt controls the frequency of both rail2, and rosc_saus controls the frequency of the rail1. single?phase rail remote sense error amplifier a high performance, high input impedance, differential transconductance amplifier is provided to accurately sense the regulator output voltage and provide high bandwidth transient performance. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points through filter networks described in the droop compensation and dac feedforward compensation sections. the remote sense error amplifier outputs a current proportional to the difference between the vsp, vsn and dac voltages: i comp gm ea v dac v vsp v vsn (eq. 14) single?phase rail voltage compensation the remote sense amplifier output current is applied to a standard type ii compensation network formed by external tuning components clf, rz and chf. vsp comp vsn clf rz chf vsn vsp dac gm figure 15. single?phase rail ? programming the dac feed?forward filter the dac feed?forward implementation for the single?phase rail is the same as for the 2?phase rail. the NCP81248 outputs a pulse of current from the vsn pin upon each increment of the internal dac following a dvid up command. a parallel rc network inserted into the path from vsn to the output voltage return sense point, vss_sense, causes these current pulses to temporarily decrease the voltage between vsp and vsn. this causes the output voltage during dvid to be regulated slightly higher, in order to compensate for the droop function response to inductor current flowing into the charging output capacitors. rffsp sets the gain of the dac feed?forward and cffsp provides the time constant to cancel the time constant of the system per the following equations. cout is the total output capacitance of the system. vsp vsn rffsp cffsp csnssp to vss_sense dac dac forward vsn vsp dac feed? dac feedforward current from svid interface gm figure 16. r ffsp loadline * cout 1.35 * 10 ?9 [ ] (eq. 15) c ffsp 200 r ffsp [nf] (eq. 16)
NCP81248 www. onsemi.com 21 single?phase rail ? differential current feedback amplifier each single?phase controller has a low offset, dif ferential amplifier to sense output inductor current. an external lowpass filter can be used to superimpose a reconstruction of the ac inductor current onto the dc current signal sensed across the inductor. to do this, the lowpass filter time constant should match the inductor l/dcr time constant by setting the filter pole frequency equal to the zero of the output inductor. this makes the filter ac output mimic the product of ac inductor current and dcr, with the same gain as the filter dc output. it is best to perform fine tuning of the filter pole during transient testing. f z dcr@25c 2* *l [hz] (eq. 17) f p 1 2* * r phsp * rth r cssp r phsp rth r cssp *c cssp [hz] (eq. 18) forming the lowpass filter with an ntc thermistor (rth) placed near the output inductor, compensates both the dc gain and the filter time constant for the inductor dcr change with temperature. the values of rphsp and rcssp are set based on the ef fect of temperature on both the thermistor and inductor, and may need to be adjusted to eliminate output voltage temperature drift with the final product enclosure and cooling.. the csp and csn pins are high impedance inputs, but it is recommended that the lowpass filter resistance not exceed 10 k in order to avoid offset due to leakage current. it is also recommended that the voltage sense element (inductor dcr) be no less than 0.5 m for sufficient current accuracy. recommended values for the external filter components are: c cssp l phase r phsp * rth r cssp r phsp rth r cssp * dcr [f] (eq. 19) ? r phsp = 7.68 k ? r cssp = 14.3 k ? rth = 100 k , beta = 4300 using two parallel capacitors in the lowpass filter allows fine tuning of the pole frequency using commonly available capacitor values. the dc gain equation for the current sense amplifier output is: v curr rth r cssp r phsp rth r cssp * iout * dcr (eq. 20) csp csn rphsp rcssp t rth ccssp inductor to current sense amp pwm generator curr _ + av=1 comp figure 17. the amplifier output signal is combined with the comp and ramp signals at the pwm comparator inputs to produce the ramp pulse modulation (rpm) pwm signal. single?phase rail ? loadline programming (droop) an output loadline is a power supply characteristic wherein the regulated (dc) output voltage decreases by a voltage (v droop ) proportional to load current. this characteristic can reduce the output capacitance required to maintain output voltage within limits during load transients faster than those to which the regulation loop can respond. in the NCP81248, a loadline is produced by adding v droop to the output voltage feedback signal ? thereby satisfying the voltage regulator at an output voltage reduced in proportion to load current. v droop is developed across a resistance between the vsp pin and the output voltage sense point by forcing current from the vsp pin that is proportional to the difference between the csp and csn voltages.
NCP81248 www. onsemi.com 22 vsp csp csn rphsp rcssp t rth ccssp inductor to rdrpsp cdrpsp csnssp to vcc_sense current sense amp vsn vsp droop current _ + av=1 gm rcdrpsp figure 18. v droop r drpsp gm vsp rth r cssp r phsp rth r cssp (eq. 21) i out dcr r drpsp loadline gm vsp dcr r phsp rth r cssp rth r cssp [ ] (eq. 22) single?phase rail ? programming iout the iout pin sources a current proportional to the voltage between the csp and csn pins. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a high?value pull?up resistor from 5 v v cc can be used to offset the iout signal positive if desired. csp csn iout rphsp rcssp t rth ccssp inductor to rioutsp monitor current current sense amp iout _ + av=1 gm figure 19. r ioutsp 2v gm iout rth r cssp r phsp rth r cssp iccmax dcr (eq. 23)
NCP81248 www. onsemi.com 23 programming the single?phase rail icc_max resistors to ground on the iccmax_1a and iccmax_1b pins program these registers for the single phase rails at the time the part is enabled. i mxbias1a and i mxbias1b currents are sourced from these pins to generate a voltage on the program resistors. the resistor value should be no less than 10k. icc_max 21h r*i mxbias1 *64a 2v (eq. 24) single?phase rail pulsewidth modulator a pwm pulse starts when the error amp output (comp voltage) exceeds a trigger threshold including a scaled inductor current (i l *dcr*phase current gain factor). the pwm pulse ends when scaled inductor current added to a compensating reset ramp exceeds the comp voltage. both edges of the pwm signals are modulated. during a transient event, the duty cycle can increase rapidly as the comp voltage increases with respect to the trigger threshold and reset ramp, to provide a highly linear and proportional response to the step load. disabling a single?phase rail if the NCP81248 is to provide fewer than three rails, either or both of the single?phase regulators can be disabled by pulling up th eir respective csp pin to vcc. the two?phase regulator cannot be disabled. protection features two?phase regulator over current protection (ocp) a programmable total phase current limit is provided that is decreased when not operating in full current mode. this limit is programmed with a resistor between the cscomp and ilim pins. the current from the ilim pin to this resistor is compared to the ilim threshold currents (i cl0 , i clm0 , i cl1 , and i clm1 ). when the 2?phase rail is operating in full current mode, if the ilim pin current exceeds i cl0 , an internal latch?off timer starts. if the fault is not removed, the controller shuts down when the timer expires. if the current into the pin exceeds i clm0 , the controller shuts down immediately. when operating in ps1, ps2, or ps3, the ilim pin current limits are i cl1 and i clm1 . to recover from an ocp fault, the en pin or v cc voltage must be cycled low. cscomp cssum csref _ + rcs2 csn2 csn1 swn1 swn2 rref2 rref1 rph1 rph2 rcs1 ccs1 ccs2 rth cref riout rilim ilim buffer iout to remote sense amplifier controller comparators current limit mirror current figure 20. use equation 10 to calculate the ilim resistor value. single?phase rail over current protection (ocp) the current limit threshold is programmed with a resistor (r ilimsp ) from the ilim pin to ground. the current limit latches the single?phase rail off immediately if the ilim pin voltage exceeds the ilim threshold voltage (v cl ). set the value of the current limit resistor based on the equation shown below.
NCP81248 www. onsemi.com 24 csp csn ilim rphsp rcssp t rth ccssp inductor to rilimsp programming comparators overcurrent overcurrent current sense amp ocp ocp ref _ + av=1 gm cilimsp figure 21. r ilimsp v cl gm ilim r th r cssp r phsp r th r cssp iout limit dcr [ ] (eq. 25) c ilimsp 5*10 7 r ilimsp [pf] (eq. 26) a capacitor (c ilimsp ) in parallel with the ilim pin resistor creates a time delay to give some tolerance for output currents that momentarily exceed the current limit. the c ilimsp value given in the equation below will give up to a 50 s delay with a 150% overload depending on the load current prior to overload. to recover from an ocp fault, the en pin or v cc voltage must be cycled low. input under?voltage lockouts (uvlo) NCP81248 monitors the 5 v v cc supply as well as the vrmp pin voltage. hysteresis is incorporated within these monitors. output under voltage monitor the 2?phase rail output voltage is monitored for undervoltage at the output of the dif ferential amplifier. if the 2?phase rail output falls more than v uvm2 below the dac?droop voltage, the uvm comparator will trip ? sending the vr_rdy signal low.the single?phase rail outputs are monitored for undervoltage at the csn inputs. if the csn voltage falls more than v uvm1 below the dac voltage, the uvm comparator will trip ? sending the vr_rdy signal low. output over voltage protection the 2?phase output voltage is monitored for ovp at the output of the differential amplifier and also at the csref pin. the single?phase regulator outputs are monitored for overvoltage at the vsp & vsn inputs, and also at the csn inputs. during normal operation, if an output voltage exceeds the dac voltage by v ovp , the vr_rdy flag goes low, and the dac voltage of the overvoltage rail will be slowly ramped down to 0 v to avoid producing a negative output voltage. at the same time, the pwm outputs of the overvoltage rail are sent low. the pwm output will pulse to mid?level during the dac ramp down period if the output decreases below the dac + ovp threshold as dac decreases. when the dac gets to zero, the pwms will be held low, and the NCP81248 will stay in this mode until the v cc voltage or en is toggled. 2.0 v ovp threshold dac+~400mv uvlo rising dron dac vcc figure 22. ovp threshold behavior
NCP81248 www. onsemi.com 25 2.0 v ovp threshold vout dac dron pwm figure 23. ovp behavior at startup during start up, the ovp threshold is set to the absolute over voltage threshold. this allows the controller to start up without false triggering ovp. dac vsp_vsn ovp threshold latch off ovp triggered pwm figure 24. ovp during normal operation mode
NCP81248 www. onsemi.com 26 typical pcb layout top layer bottom layer viewed from top pin 1 figure 25.
NCP81248 www. onsemi.com 27 package dimensions qfn48 6x6, 0.4p case 485ba issue a seating note 4 k 0.10 c (a3) a a1 d2 b 1 13 25 48 2x 2x e2 48x l bottom view detail a top view side view d a b e 0.10 c pin one location 0.10 c 0.08 c c 37 e a 0.07 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.15 0.25 d 6.00 bsc d2 4.40 4.60 e 6.00 bsc 4.60 e2 4.40 e 0.40 bsc l 0.30 0.50 l1 0.00 0.15 note 3 plane dimensions: millimeters 0.25 4.66 0.40 4.66 48x 0.68 48x 6.40 6.40 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* e/2 detail b l1 detail a l alternate terminal constructions l 0.20 min pitch 48x pkg outline on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81248/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative intel is a registered trademark of intel corporation in the u.s. and/or other countries.

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